1. Field of the Invention
The present invention generally relates to a memory structure, in particular, to a memory structure having reduced standby current and low power consumption.
2. Description of Related Art
Dynamic random access memory (DRAM) is adopted in many electronic system products as the optimal and indispensable memory solution due to its advantages of low cost and large volume. Presently, DRAM is mainly used in information products, such as desktop computers, notebook computers, DRAM upgrade modules, servers, and workstations etc.
Supply voltage VDD in DRAM has been lowered along with the advancement of fabricating process and increasing demand to low power consumption. However, voltage VPP for turning on word lines in memory cells is still higher than the supply voltage VDD. Accordingly, a voltage booster is required for boosting the supply voltage VDD up to the word line voltage VPP.
Generally speaking, a voltage booster includes a plurality of voltage pumps. Since the supply voltage VDD is being developed lower and lower, the number of voltage pumps used for voltage boosting is getting more and more. However, a large number of voltage pumps may reduce pump efficiency. Pump efficiency PE is defined as following:PE=I—VPP/I—VDD   (1)
In the above formula, I_VDD represents current provided by the power supply, and I_VPP represents current provided by the voltage pumps.
In addition, a memory which is not in operation will be switched to a standby state so as to reduce the power consumption thereof. A high standby current also causes unnecessary power consumption when a memory is in standby state. Moreover, reduced pump efficiency may further increase the standby current and accordingly the power consumption.
Accordingly, a voltage booster having high pump efficiency, low standby current, and reduced power consumption and a memory structure using the voltage booster are provided by the present invention.